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Microchip Technology /ATSAME51N20A /CoreDebug /DEMCR

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Interpret as DEMCR

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https://regviz.com/r/Microchip Technology/ATSAME51J19A/CoreDebug/DEMCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VC_CORERESET)VC_CORERESET 0 (VC_MMERR)VC_MMERR 0 (VC_NOCPERR)VC_NOCPERR 0 (VC_CHKERR)VC_CHKERR 0 (VC_STATERR)VC_STATERR 0 (VC_BUSERR)VC_BUSERR 0 (VC_INTERR)VC_INTERR 0 (VC_HARDERR)VC_HARDERR 0 (MON_EN)MON_EN 0 (MON_PEND)MON_PEND 0 (MON_STEP)MON_STEP 0 (MON_REQ)MON_REQ 0 (TRCENA)TRCENA

Description

Debug Exception and Monitor Control Register

Fields

VC_CORERESET
VC_MMERR
VC_NOCPERR
VC_CHKERR
VC_STATERR
VC_BUSERR
VC_INTERR
VC_HARDERR
MON_EN
MON_PEND
MON_STEP
MON_REQ
TRCENA

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data